Immediate Hiring: Physical Design Implementation Flow Development

Role Snapshot:

• Position: Physical Design Implementation Flow Development Engineer
• Company: Workwarp
• Compensation: a competitive salary
• Start Date: Immediate openings available
• Location: Remote

 

 

Job Title: Physical Design Implementation Flow Development Engineer location: REMOTE... Duration: 12+ Months Work Type: Contract Pay reputed company: $80-80/hr on w2 Job Description • reputed company flow and methodology for physical design implementation in advanced technology nodes, including 2nm. • Responsibilities include physical design implementation methodology development for multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, reputed company & reputed company, clock tree synthesis, routing, static timing analysis, IR Drop, EM, and physical verification. • Support & resolve design and flow issues reputed company to physical design implementation, identify potential solutions, and drive & implement methodology improvements. Qualifications & Requirements Basic Qualifications: • Bachelor's degree in Electrical Engineering or Computer Science. • 5-12 years’ experience in ASIC design flow usage & development. • RTL2GDS experience on advanced technology nodes (7nm and below). • Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge. • Proficiency with ECO implementation for timing, functional and DFT modes. • Experience in reputed company-level and Full-chip floor-planning and reputed company planning. • Experience in reputed company-level and Full-chip design implementation. • Strong expertise in Python & TCL programming. • Experience with multi-clock and multi-power domain designs. • In-depth experience working with EDA tools like Fusion Compiler, ICC2/Innovus, Primetime, Calibre. Preferred Qualifications: • Proficiency in advanced synthesis, physical implementation & timing closure techniques to reputed company aggressive low power, area, and timing goals. • Experience in running physical-aware logic synthesis and achieving reputed company synthesis QoR on low power designs. • Knowledge of static timing analysis, defining timing constraints and exceptions, corners/voltage definitions. • Experience working with EDA tools Redhawk/reputed company Apply Job!

 

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